CHIPSEL         Name
 ---------|-----------------
   1  1		TA-1
   2  2		TA-2
   3  3		TA-3
   4  4		TA-4
   5  5		TB-1
   6  6		TB-2
   7  7		TC-1
   8  8		TC-2
   9  9		Route-1 (bits 7..0)
  10  A		Route-2 (bits 15..8)
  11  B		Route-3 (bits 23..16)
  12  C		Pre-Scaler-1 (3..0)
  13  D		Pre-Scaler-2 (7..4)
  14  E		Pre-Scaler-3 (11..8)
  15  F		Pre-Scaler-4 (15..12)
  16 10		Pre-Scaler-5 (19..16)
  17 11		Pre-Scaler-6 (23..20)
  18 12		Scaler-1 (3..0)
  19 13		Scaler-2 (7..4)
  20 14		Scaler-3 (11..8)
  21 15		Scaler-4 (15..12)
  22 16		Scaler-5 (19..16)
  23 17		Scaler-6 (23..20)
  24 18		Bunch-finder

  Address bits 
 1 (0x04)  5  write/read CHIPSEL register 
 2 (0x08)  3  write/read SELCHAN register
 3 (0x0C)  6  write/read route register (SELCHAN/CHIPSEL). Uses data[29..24].
 4 (0x10) 24  write/read prescale register (SELCHAN/CHIPSEL)
 5 (0x14) 24  latch/read prescale counter outputs (SELCHAN/CHIPSEL)
 6 (0x18)  0  send clear pulse to clear (restart) prescalers (on write cycle)
 7 (0x1C)  2  write/read scaler SELDAT register
 8 (0x20) 16  latch/read scaler word (SELDAT/SELCHAN/CHIPSEL)
 9 (0x24)  0  increment scaler (SELCHAN/CHIPSEL)
10 (0x28)  0  clear scaler (SELCHAN/CHIPSEL)
11 (0x2C)  0  clear all scalers
12 (0x30)  8  write/read cpu trigger register (2 bits each to TA1, TA2, TA3, TA4 [lsb-msb] )
13 (0x34)  8  write/read cpu inhibit register (2 bits each to TB1, TB2, TC1, TC2 [lsb-msb] )
14 (0x38)  1  write/read bunch reject register (when low all bunches kept-default) (bit)
15 (0x3C)  1  write/read cpu-accept register (will send a single l1accept pulse when set) (bit)
16 (0x40)  1  write/read SDR, serial direction register (bit)
17 (0x44)  1  write/read serial clock and data[30] (CHIPSEL)
              On Write: if SDR is high, data[30] is written into top of
                serial shift register; if SDR is low, register is rotated one step.
              On Read: if SDR is low, bottom of shift register is read to data[30].
                If SDR is high, shift register bits are moved to local latches accompanying
                each shift register (these latched bits are used on chip, not the SR bits)
18 (0x48)  0  clear/reset all scalers and prescalers (on write)
19 (0x4C)  0  capture (snapshot) all scalers and prescalers (on write)